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ics813n252i-02 data sheet ics813n252aki-02 revision b may 27, 2011 1 ?2011 integrated device technology, inc. jitter attenuator & femtoclock ng ? multiplier general description the ics813n252i-02 device uses idt's fourth generation femtoclock ? ng technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. the ics813n252i-02 is a pll based synchronous multiplier that is optimized for pdh or sonet to ethernet clock jitter attenuation and frequency translation. theics813n252i-02 is a fully integrated phase locked loop utilizing a femtoclock ng digital vcxo that provides the low jitter, high frequency sonet/pdh output clock that easily meets oc-48 jitter requirements. this vcxo technology simplifies pll design by replacing the pullable crystal requirement of analog vcxos with a fixed 27mhz generator crystal. jitter attenuation down to 10hz is provided by an external loop filter. pre-divider and output divider multiplication ratios are selected using device selection control pins. the multiplication ratios are optimized to support most common clock rates used in pdh, sonet and ethernet applications. the device requires the use of an external, inexpensive fundamental mode 27mhz crystal. the device is packaged in a space-saving 32-vfqfn package and supports industrial temperature range. features ? fourth generation femtoclock? ng technology two lvpecl output pairs each output supports independent frequency selection at 25mhz, 125mhz, 156.25mhz and 312.5mhz two differential inputs support the following input types: lvpecl, lvds, lvhstl, sstl, hcsl accepts input frequencies from 8khz to 155.52mhz including 8khz, 1.544mhz, 2.048mhz, 19.44mhz, 25mhz, 77.76mhz, 125mhz and 155.52mhz crystal interface optimized for a 27mhz, 10pf parallel resonant crystal attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal customized settings for jitter attenuation and reference tracking using an external loop filter connection femtoclock ng frequency multiplier provides low jitter, high frequency output absolute pull range: 100ppm power supply noise rejection (psnr): -95db (typical) femtoclock ng vcxo frequency: 2500mhz rms phase jitter @ 156.25mhz, using a 27mhz crystal (12khz ? 20mhz): 0.6ps (typical) rms phase jitter @ 125mhz, using a 27mhz crystal (12khz ? 20mhz): 0.63ps (typical) 3.3v supply voltage -40c to 85c ambient operating temperature available in lead-free (rohs 6) package 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 lf1 lf0 iset v ee clk_sel v cc reserved v ee v ee nqb qb v cco nqa qa v ee odasel_0 pdsel_2 pdsel_1 pdsel_0 v cc v cca odbsel_1 odbsel_0 odasel_1 xtal_in xtal_ou t clk0 nclk0 v cc clk1 nclk1 v ccx pin assignment ics813n252i-02 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
ics813n252aki-02 revision b may 27, 2011 2 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier block diagram phase detector + charge pump a/ d control block femtoclock ng vco na fractional feedback divider pd + lf m xtal osc. lf0 lf1 iset qa, nqa qb, nqb 0 1 p clk_sel pdsel _[2:0] nb odbsel _[1:0] odasel _[1:0] 27mhz *** dashed lines indicates external components digital vcxo pulldown pullup / pulldown pullup / pulldown pulldown pullup pulldown 3 clk0 , nclk0 clk1 , nclk1 pulldown 2 2 pulldown
ics813n252aki-02 revision b may 27, 2011 3 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 lf1, lf0 analog input/output loop filter connection node pins. lf0 is the output. lf1 is the input. 3 iset analog input/output charge pump current setting pin. 4, 8, 18, 24 v ee power negative supply pins. 5 clk_sel input pulldown input clock select. when high selects clk1, nclk1. when low, selects clk0, nclk0. lvcmos / lvttl interface levels. 6, 12, 27 v cc power core supply pins. 7 reserved reserve reserved pin. 9, 10, 11 pdsel_2, pdsel_1, pdsel_0 input pullup pre-divider select pins. lvcmos/lvttl interface levels. see table 3a. 13 v cca power analog supply pin. 14, 15 odbsel_1, odbsel_0 input pulldown frequency select pins for bank b output. see table 3b. lvcmos/lvttl interface levels. 16, 17 odasel_1, odasel_0 input pulldown frequency select pins for bank a output. see table 3b. lvcmos/lvttl interface levels. 19, 20 qa, nqa output differential bank a clock outputs. lvpecl interface levels. 21 v cco power output supply pin. 22, 23 qb, nqb output differential bank b clock outputs. lvpecl interface levels. 25 nclk1 input pullup/ pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 26 clk1 input pulldown non-inverting differential clock input. 28 nclk0 input pullup/ pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 29 clk0 input pulldown non-inverting differential clock input. 30, 31 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input. xtal_out is the output. 32 v ccx power power supply pin for the crystal oscillator. symbol parameter test conditions minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics813n252aki-02 revision b may 27, 2011 4 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier function tables table 3a. pre-divider selection function table table 3b. output divider function table note: x denotes a or b. inputs p value pdsel_2 pdsel_1 pdsel_0 000 1 001 193 010 256 011 1944 100 2500 101 7776 1 1 0 12500 1 1 1 15552 (default) inputs nx value odxsel_1 odxsel_0 0 0 100 (default) 01 20 10 16 11 8
ics813n252aki-02 revision b may 27, 2011 5 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier table 3c. frequency function table note: x denotes a or b. input frequency (mhz) p value femtoclock ng vcxo center frequency (mhz) nx value output frequency (mhz) 0.008 1 2500 100 25 0.008 1 2500 20 125 0.008 1 2500 16 156.25 0.008 1 2500 8 312.5 1.544 193 2500 100 25 1.544 193 2500 20 125 1.544 193 2500 16 156.25 1.544 193 2500 8 312.5 2.048 256 2500 100 25 2.048 256 2500 20 125 2.048 256 2500 16 156.25 2.048 256 2500 8 312.5 19.44 1944 2500 100 25 19.44 1944 2500 20 125 19.44 1944 2500 16 156.25 19.44 1944 2500 8 312.5 25 2500 2500 100 25 25 2500 2500 20 125 25 2500 2500 16 156.25 25 2500 2500 8 312.5 77.76 7776 2500 100 25 77.76 7776 2500 20 125 77.76 7776 2500 16 156.25 77.76 7776 2500 8 312.5 125 12500 2500 100 25 125 12500 2500 20 125 125 12500 2500 16 156.25 125 12500 2500 8 312.5 155.52 15552 2500 100 25 155.52 15552 2500 20 125 155.52 15552 2500 16 156.25 155.52 15552 2500 8 312.5
ics813n252aki-02 revision b may 27, 2011 6 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvpecl power supply dc characteristics, v cc = v cco = v ccx = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c item rating supply voltage, v cc 3.63v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ja 33.1 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v v ccx crystal supply voltage 3.135 3.3 3.465 v i ee power supply current 273 ma i cca analog supply current 30 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_sel, odasel_[1:0], odbsel_[1:0] v cc = v in = 3.465v 150 a pdsel_[2:0] v cc = v in = 3.465v 10 a i il input low current clk_sel, odasel_[1:0], odbsel_[1:0] v cc = 3.465v, v in = 0v -10 a pdsel_[2:0] v cc = 3.465, v in = 0v -150 a
ics813n252aki-02 revision b may 27, 2011 7 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier table 4c. differential dc characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2. common mode voltage is defined at the crosspoint. table 4d. lvpecl dc characteristics, v cc = v cco = v ccx = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco ? 2v. see parameter measurement information section, 3.3v output load test circuit. symbol parameter test conditions minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v cc = v in = 3.465v 150 a i il input low current clk0, clk1 v cc = 3.465v, v in = 0v -10 a nclk0, nclk1 v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak input voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee v cc ? 0.85 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.10 v cco ? 0.75 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v
ics813n252aki-02 revision b may 27, 2011 8 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier ac electrical characteristics table 5. ac characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized with outputs at the same frequency using the loop filter components for the 35hz loop bandwidth. refer to jitter attenuator loop bandwidth selection table. note 1: refer to the phase noise plot. note 2: psnr results achieved by injecting noise on v cca supply pin with no external filter network. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. note 5: lock time measured from power-up to stable output frequency. symbol parameter test conditions minimum typical maximum units f in input frequency 0.008 155.52 mhz f out output frequency 25 312.5 mhz t jit(?) rms phase jitter, (random), note 1 125mhz f out , 27mhz crystal, integration range: 12khz ? 20mhz 0.63 ps 156.25mhz f out , 27mhz crystal, integration range: 12khz ? 20mhz 0.6 ps psnr power supply noise rejection; note 2 v pp = 50mv sine wave, range: 10khz ? 10mhz -95 db t sk(o) output skew; note 3, 4 80 ps t r / t f output rise/fall time 20% to 80% 150 450 ps odc output duty cycle 48 52 % t lock output-to-input phase lock time; note 5 reference clock input is 100ppm from nominal frequency 4s
ics813n252aki-02 revision b may 27, 2011 9 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier typical phase noise at 125mhz noise power dbc hz offset frequency (hz)
ics813n252aki-02 revision b may 27, 2011 10 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier parameter measurement information 3.3v lvpecl output load ac test circuit output-to-input phase lock time output skew output duty cycle/pulse width/period differential input level rms phase jitter lvpecl output rise/fall time scope qx nqx lvpecl v ee 2v -1.3v 0.165v v cc, v cco, v cca v ccx 2v lock time not to scale v cc v ee supply voltage output 60% of v cc output-to-input phase lock t sk(o) qx nqx qy nqy nqa, nqb qa, qb t pw t period t pw t period odc = x 100% nclk[0:1] clk[0:1] v cc v ee v cmr cross points v pp offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power 20% 80% 80% 20% t r t f v swing qa, qb nqa, nqb
ics813n252aki-02 revision b may 27, 2011 11 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels
ics813n252aki-02 revision b may 27, 2011 12 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver figure 2f. clk/nclk input driven by a 2.5v sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 ? lvds clk nclk 3.3v receive r zo = 50 ? zo = 50 ? clk nclk differential input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ?
ics813n252aki-02 revision b may 27, 2011 13 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination f igure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics813n252aki-02 revision b may 27, 2011 14 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier jitter attenuator e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the jitter attenuator. in choosing a crystal, special precaution must be taken with load capacitance (c l ), frequency accuracy and temperature range. the crystal?s c l characteristic determines its resonating frequency and is closely related to the center tuning of the crystal. the total external capacitance seen by the crystal when installed on a pcb is the sum of the stray board capacitance, ic package lead capacitance, internal device capacitance and any installed tuning capacitors (ctune). the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve for a typical pcb. if the crystal c l is greater than the total external capacitance, the crystal will oscillate at a higher frequency than the specification. if the crystal c l is lower than the total external capacitance, the crystal will oscillate at a lower frequency than the specification. tuning adjustments might be required depending on the pcb parasitics or if using a crystal with a higher c l specification. in addition, the frequency accuracy specification in the crystal characteristics table are used to calculate the apr (absolute pull range). crystal characteristics the vcxo-pll loop bandwidth selection table shows rs, cs,cp and rset values for recommended high, mid and low loop bandwidth configurations. the device has been characterized using these parameters. in addition, the digital vcxo gain (kvcxo) has been provided for additional loop filter requirements. jitter attenuator characteristics table jitter attenuator loop bandwidth selection table the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. lf0 lf1 iset xtal_in xtal_out r s c s c p r set c tune c tune 27mhz symbol parameter test conditions minimum typical maximum units mode of oscillation fundamental f n frequency 27 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range -40 +85 0 c c l load capacitance 10 pf c o shunt capacitance 4pf esr equivalent series resistance 40 ? drive level 1mw aging @ 25 0 c first year 3 ppm symbol parameter typical units k vcxo vcxo gain 2.76 khz/v bandwidth crystal frequency r s (k ? )c s (f) c p (f) r set (k ? ) 7hz (low) 27mhz 110 10 0.01 2.21 35hz (mid) 27mhz 365 1 0.002 1.5 45hz (high) 27mhz 470 1 0.0005 1.5
ics813n252aki-02 revision b may 27, 2011 15 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics813n252aki-02 revision b may 27, 2011 16 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier schematic example figure 5 (on next page) shows an example of ics813n252i-02 application schematic. in this example, the device is operated at v cc = v ccx = v cco = 3.3v. a 10pf parallel resonant 27mhz crystal is used. spare placement pads for the load capacitance c1 and c2 are recommended for frequency accuracy. depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. this will required adjusting c1 and c2. an optional 3-pole filter can also be used for additional spur reduction. it is recommended that the loop filter components be laid out for the 3-pole option. this will allow the flexibility for the 2-pole filter to be used. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ics813n252i-02 provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
ics813n252aki-02 revision b may 27, 2011 17 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier figure 5. ics813n252i-02 schematic example odbsel_0 lf set logic input to '0' + - c5 10u r14 1.5k odbsel_1 zo = 50 qb c4 0.1u c5 0.1uf lvpecl optional y-termination qa to logic input pins c6 10uf lf r9 133 rs 365k vcco c6 0.1u cp 0.002uf odasel_1 r10 133 c10 10u pdsel_2 zo = 50 ohm r13 82.5 xtal_ ou t nclk1 c5 0.1uf nqb r5 125 rd2 1k nclk1 r1 125 clk1 vcc c7 0.1u u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 lf1 lf0 iset vee clk_sel vcc reserved vee pdsel2 pdsel_1 pdsel_0 vcc vcca odbsel_1 odbsel_0 odasel_1 odasel_0 vee qa nqa vcco qb nqb vee vccx xtal_in xtal_out clk0 nclk0 vcc clk1 nclk1 vcc xtal_ i n nqa lf 3.3v vcc zo = 50 10pf r3 820k 3.3v vccx r18 50 + - ru2 not install c1 tu n e r2 125 2-pole loop filter for mid bandwidth setting nclk0 r8 85 clk_sel set logic input to '1' vcca clk0 clk1 c11 0.1u vcc cs 1uf zo = 50 vcc r12 82.5 zo = 50 ohm cp 0.002uf vcc rd1 not install x1 27mhz c8 0.1u zo = 50 ohm zo = 50 ohm r16 50 pdsel_1 zo = 50 to logic input pins c2 tu n e lvpecl driv er r6 125 c3 220pf vcc odasel_0 c6 10uf r7 84 c9 0.1u vcc r11 10 logic control input examples 3.3v lvpecl terminat ion r19 10 clk0 pdsel_0 nclk0 3-pole loop filter example - (optional) blm18bb221sn1 ferrite bead 1 2 r15 50 lvpecl driv er blm18bb221sn1 ferrite bead 1 2 r4 84 cs 1uf rs 365k vcc lf ru1 1k r20 84
ics813n252aki-02 revision b may 27, 2011 18 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier power considerations this section provides information on power dissipation and junction temperature for the ics813n252i-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics813n252i-02 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cco = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cco_max * i ee_max = 3.465v * 273ma = 945.945mw power (outputs) max = 31.55mw/loaded output pair if all outputs are loaded, the total power is 2 * 31.55mw = 63.1mw total power_ max (3.3v, with all outputs switching) = 945.945mw + 63.1mw = 1009.045mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c +1.009w * 33.1c/w = 118.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 32 lead vfqfn, forced convection ja by velocity meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
ics813n252aki-02 revision b may 27, 2011 19 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. for logic high, v out = v oh_max = v cco_max ? 0.75v (v cc_max ? v oh_max ) = 0.75v for logic low, v out = v ol_max = v cco_max ? 1.6v (v cc_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v? 0.75v)/50 ? ] * 0.75v = 18.75mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.6v)/50 ? ] * 1.6v = 12.80mw total power dissipation per output pair = pd_h + pd_l = 31.55mw v out v cco v cco - 2v q1 rl 50 ?
ics813n252aki-02 revision b may 27, 2011 20 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier reliability information table 7. ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ics813n252i-02 is: 44,832 ja vs. air flow meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
ics813n252aki-02 revision b may 27, 2011 21 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 8. package dimensions note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8. reference document: jedec publication 95, mo-220 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge a re: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics813n252aki-02 revision b may 27, 2011 22 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 813N252AKI-02LF ics252ai02l ?lead-free? 32 lead vfqfn tray -40c to 85c 813N252AKI-02LFt ics252ai02l ?lead-free? 32 lead vfqfn 2500 tape & reel -40c to 85c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics813n252aki-02 revision b may 27, 2011 23 ?2011 integrated device technology, inc. ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier revision history sheet rev table page description of change date a 11 16 - 17 deleted power supply filtering technique application section (included in schematic application). updated schematic application. 1/14/11 a 16 - 17 updated schematic application with 10pf from 12pf. 2/8/11 a 6 supply voltage, v cc. rating changed from 4.5v min. to 3.63v per errata nen-11-03. 5/20/11 b 2 correct typo in block diagram from /2 to /3 for pdsel[2:0] 5/27/11
ics813n252i-02 data sheet jitter attenuator & femtoclock ng ? multiplier disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of any kind, whether e xpress or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an imp lied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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